Zero ASIC was founded in 2008 as Adapteva, a parallel processor startup, and relaunched as Zero ASIC in Feb 2020 to “remove the barrier to custom silicon.” The company’s mission is now to “remove the barriers to custom silicon.” The company is backed by government contracts and has roughly 18 employees.

Zero ASIC’s business model is to design and sell SiP devices leveraging its chiplet-based design automation technology. The company created SiliconCompiler, an open-source modular build system for hardware (“make for silicon’).

The company recently unveiled three chiplets: Gotland, a quad-core RV64GC CPU based on UC Berkeley’s Rocket Chip RISC-V SoC generator, Maui FPGA and Kodiak 3MB memory. All chiplets measure 2mm2.

Zero ASIC is planning a public launch this fall.

Andreas Olofsson, Founder & CEO (previously Program Manager at DARPA focused on chip design and automation, founder and CEO of Adapteva, and Senior Architect at Analog Devices)

Amir Volk, VP of Hardware Engineering (previously Senior director, IP development at Intel)

andreas@zeroasic.com