Ayar Labs (formerly OptiBit, see 2/18 issue) was founded in May 2015 to improve the speed and energy efficiency of high performance computing (HPC) systems with silicon chips that transmit data using light. The company was formed by the inventors of the first microprocessor chip to communicate using light at MIT, UC Berkeley, and CU Boulder, a breakthrough that was the result of a 10-year research collaboration funded by DARPA.
In 2015, the company won MIT's Clean Energy Prize (CEP) competition, earning a total of $275,000. The company raised $2.5 million in seed funding from FF Science, part of Founders Fund, and TechU Angels, and is a graduate of the Silicon Catalyst incubator. In Nov. 2018, Ayar raised $24M in Series A funding from Playground Global, Founders Fund, GlobalFoundries and Intel Capital.
Today, most silicon photonics companies compete with traditional optics companies in the long-distance communications arena. In contrast, Ayar is targeting shorter-distance copper interconnects for within-rack (<3 m) and within-board (<1 m) communications. The initial company focus is the HPC market where its optical I/O can carry >10x more data than copper pins. The TAM for inter-chip optical interconnect is 4x the optical transceiver market, according to Ayar.
Ayar’s optical devices are 100x smaller than those used by other silicon photonic companies, according to the company. This enables the company to create optical I/O systems that are 10x smaller than their electrical SerDes counterparts. Its solution offers 10x higher chip area bandwidth density, 10x higher chip edge bandwidth density, and 5-10x lower power consumption than today’s electrical SerDes copper interconnects.
Ayar Labs uses industry standard silicon processing techniques to develop high speed, high density, low power optical-based interconnect “chiplets” and lasers. GLOBALFOUNDRIES and Ayar Labs have a strategic collaboration to co-develop and commercialize silicon photonic solutions. As part of the agreement, GF has invested an undisclosed amount in Ayar. The Ayar team has been designing silicon photonics components on GF’s technology for the past eight years. The companies will develop and manufacture Ayar’s CMOS optical I/O technology using GF’s 45nm CMOS process.
Ayar’s optical chiplet will be integrated in the existing multi-chip-module ecosystem, enabling high-bandwidth, low-latency, low-power optical communications directly from partner chips. Ayar has targeted the AL10 design, its 10th generation electrical to optical I/O chiplet, due to tape-out end of Q1’19, as the company’s first broadly available commercial product. Named TeraPHY, it will be integrated with other partners’ designs into multi-chip module computing products available in 2020, enabling optical I/O bandwidth capability in excess of a Terabit/sec at 10X lower power than today’s Gigabit/sec I/O solutions.
The Ayar Labs Brilliant™ connectivity system is comprised of TeraPHY silicon chips, SuperNova light supplies and system reference designs. The TeraPHY silicon chip will be available in 1.6 Tbps and 3.2 Tbps versions, transmitting data on four or eight single-mode (SM) fibers respectively, each transmitting data at 400 Gbps, and receiving the same bandwidth on four or eight SM fibers.
The electrical interface will be via 50 Gbps very short reach (VSR) links. TeraPHY can interface with the customer chip via either on-board or in-package electrical traces. Optical connectivity is via standard duplex LC connectors. A separate SuperNova light supply module supplies light to the TeraPHY silicon chip via four additional fibers.
All electrical and optical I/O functionality, except for the light source, is included in the TeraPHY chip. It integrates a 50 Gbps VSR electrical interface, optical modulators, photodetectors, dense wavelength division multiplexing (DWDM) mux and demux, closed-loop thermal tuning of optical components, driver circuitry, high-speed PLL and clocking, built-in self test (BIST), and a low speed digital interface for diagnostics and control.
The SuperNova light supply is a photonic integrated circuit (PIC) that generates eight or sixteen wavelengths of O-band light (1260-1360nm), muxes them, splits the power, and amplifies it to eight or sixteen output ports. It is capable of supplying light for 256 channels of data, or 6.4 Tbps at up to 2km.
Charlie Wuischpard, CEO (most recently VP/GM in the Intel Data Center Group)
Alexandra Wright-Gladstein, Co-Founder and Chief Strategy Officer (Founding CEO, Energy Entrepreneurship Leader at MIT, Associate Program Manager, Energy Efficiency at EnerNOC)
Mark Wade, Ph.D., Co-Founder, President and Chief Scientist (previously a research affiliate at MIT)
Chen Sun, Ph.D., Co-Founder and CTO (previously a graduate research assistant at MIT)
Vladimir Stojanovic, Chief Architect and Co-Founder (associate professor of EECS at UC Berkeley, one of the key developers of the Rambus high-speed link technology)
Roy Meade, VP of Manufacturing (previously Senior Member of Technical Staff - Sr. Program Manager at Micron)
Hugo Saleh, VP of Marketing and Business Development (former Senior Director Strategic Accounts at Intel)
Lisa Cummins, Chief Financial and Operating Officer (former CFO of Penguin Computing)
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