Zocalo Technology was founded in 2006 to provide EDA solutions that increase productivity for engineers adopting and utilizing Assertion Based Verification (ABV). The company is self funded and has four full-time employees.

Assertions are properties or facts describing the required and forbidden behavior of a design. They are “executable specifications” that are monitored during simulation by assertion checkers included in the design file. The prevalent language for writing assertions is SystemVerilog Assertion (SVA) language, a specialized subset of SystemVerilog.

Various studies have shown that using ABV can reduce debug, now representing 60% of the functional verification time and cost, by 50%. However, in spite of the promise of ABV, wide scale use has not materialized. ABV is a difficult technology to implement and is perceived as marginally cost effective.

Most experts agree that assertion checkers added by designers have significant impact on detecting problems early in the functional verification process. The designer is the most familiar with the intent and limitations of the design and is in the best position to define where they are needed during simulation. Additionally, with checkers in place, formal verification can begin at the earliest stage and at the “sweet spot” for formal verification.

Nearly all designers can add assertion checkers manually on an adhoc basis. However, this rarely happens because the time required for creating, debugging, attaching and documenting them is difficult to justify when considering the typical chip design schedule. The availability of assertion libraries reduces that time, but not nearly enough for wide scale use by designers.

Zocalo is focused on software for implementing a systematic methodology for ABV. Its products enable quick and easy creation, use and reuse of assertion checkers, working seamlessly with any verification flow. The Zocalo product set, branded under the name Zazz, has been designed to increase productivity for engineers adopting and utilizing ABV.

Zazz is the first EDA software product to make using assertion libraries quick, easy and accurate by automating tedious error prone tasks with its easy to use intuitive Graphical User Interface. With Zazz, the checkers from the most widely used assertion libraries can be attached to a design and documented in minutes.

With Zazz, attaching and documenting the library checkers that cover most of the designer’s requirements, takes less than a minute each. This level of productivity and the low cost of Zazz make designer provided assertions highly effective.

Zazz Bird Dog addresses the issues of indentifying assertion candidates and providing metrics meaningful to the project.

Zazz OVL makes using assertion libraries easy including the automatic creation of bind files and documentation.

Zazz Visual SVA addresses the issues of coding and debugging complex SVAs, controlling the use of assertions from the testbench environment and automatic creation of bind files and documentation.

All three products are available standalone or combined. The design database support and design viewer are common to all Zazz products.

Zazz is Linux-based and supports any mix of Verilog 1995, Verilog 2001 and SystemVerilog design files. Support is provided for Accellera’s Open Verification Library (OVL), Cadence’s Incisive Assertion Library (IAL), Mentor’s Questa Verification Library (QVL) and Synopsys’ SystemVerilog Assertions Checker Library with Coverage Level Reporting. Zazz is available now and is $4950 for a one-year subscription.

Howard Martin, President (Previously founder and President of SpeedGate, an EDA company providing RTL partitioning for FPGA prototyping that was acquired by Mentor Graphics in 2000. Also held positions with Recal Redac, Quickturn and Aptix and was VP of Sales at Scientific and Engineering Software, now Hyperformix. After the merger of ECAD and SDA to form Cadence he was Western Area Director.)

Khalil Shalish, CTO (previously a founder of SpeedGate)

David Stevens, VP of Operations (previously cofounder of SpeedGate, emulation consulting engineer at Aptix, an individual contributor at Cadence and GM of the PCB Division at Daisy Systems)