3Plus1 Technology (see 9/04 issue) was founded in 2003 to develop “an advanced multiprocessor architecture conceived from the ground up to run next-generation handheld systems.” The founders have financed the company since its inception, with additional income from customer investment. The company will be seeking venture capital in the future.. 3Plus1 has roughly 15 employees.

3Plus1 has created a methodology and architectural approach specifically designed for low-power, concurrent execution of specific applications, including MPEG 2/4, H.263/4, JPEG/2000, 802.11 a/b/g/n, 802.16, Bluetooth, UWB, GSM/GPRS/EDGE, CDMA 2000/WCDMA, MP3, AAC, DVB-H and GPS, in a modular, scalable, heterogeneous multiprocessor architecture. The technology enables software implementation of combinations of these multi-mode scenarios and uses models that can be implemented in a sub-100mw processor core in a standard 90nm low power CMOS process.

3Plus1 recently introduced its first-generation CoolProcessor technology in the form of CoolEngine IP cores for multimedia and communications SoCs targeting mobile consumer products. The first instances of the CoolEngine family comprise two members that take advantage of the intrinsic scaling of the 3Plus1 multiprocessor approach for implementation of JPEG, MPEG, H.263, and H.264 encode and decode operations as well as standard audio applications, GPS and Bluetooth.

The CoolEngine family of cores is scalable and upwardly code-compatible with a single programming model. The company’s internally developed and automated methodology is capable of generating RTL, simulation, analysis, and verification tools from an internal design language for the CoolProcessor Architecture. Development of software applications follows a standard DSP tool flow.

The CoolEngine family is an scalable set of processor IP that can concurrently run multi-mode CODECs (CODECs and MODEMs) for multimedia and communications applications at close to ASIC efficiencies, according to the company. The CoolEngine-1010 and CoolEngine-1020, the first two CoolEngine processor IPs from 3Plus1’s first generation family are targeted for video/audio codec applications. These IPs include a CoolDMA and master/slave interface ready to be connected to all standard SoC buses including AHB Bus, AXI Bus and Sonics Interconnect.

The CoolEngine-I family is capable of running concurrent set of applications including Video Codec, WMV D1 decoding/encoding, Video pre/post processing, Audio Codec, Image Codec, and Image Signal Processing Algorithms.

Working with strategic customers, CoolEngine has shown up to 2X area and power advantages over leading configurable processor approaches and shows near-ASIC like efficiencies in a fully programmable architecture.

The company is currently delivering its initial applications-development software and FPGA Emulator Boards to strategic customers. The CoolEngine-1010 and CoolEngine-1020 IP cores are currently available and have been shipped to customers. Future products will incorporate another processor core, making the devices better suite for combined codec/modem applications.

Allan Cox, President, CEO, and Co-founder (previously COO at Quicksilver Technology and SVP of Systems IC Business Unit at Toshiba America Electronic Components)

Dr. Amir Zarkesh, EVP, Engineering, and Co-founder (previously Director of Hardware Engineering at QuickSilver and founder and CEO of ZAIAS)

Amit Ramchandran, VP, Engineering, and Co-founder (previously an architect and designer of an adaptive processor, at Quicksilver)

Ron Adolphson, Treasurer (previously CFO of BayStone Software, until its sale to Remedy)