Update: Abound Logic is introducing a new family of 65nm FPGAs that surpasses in capacity even the most optimistic projections of what others could achieve in 40nm.

M2000 was founded in 1996 by three EDA veterans, all founders of Meta Systems, which was acquired by Mentor in May 1996. At Meta Systems, they developed SIMEXPRESS, an emulation system based on custom FPGAs. M2000 initially focused on continuing the defense activities of Meta Systems; however, since 1999, the company has concentrated on the development of embedded FPGA macros.

M2000’s current vision is “to design and develop state of the art configurable logic technology for the rapidly growing reprogrammable SoC market.” M2000’s founders have worked together for more than 17 years and hold numerous patents in the field of reprogrammable logic and its applications to electronic design emulation. The company has 15 employees.

Embedded FPGA cores from M2000 are IP macros designed to be included in ASIC, SoC and ASSP circuits. The result is a hybrid chip which combines the features of an FPGA with those of an ASIC, SoC or ASSP circuit. This provides the architectural density of a custom chip with the flexibility of an FPGA.

M2000 FlexEOS is a family of logic re-programmable IP cores based on a patented architecture. FlexEOS enables designers to reconfigure and change logic function blocks in silicon by using software tools only. The FlexEOS IP family includes a series of hard macro SRAM-based re-programmable logic blocks with different sizes and portable to various silicon technologies.

FlexEOS uses an innovative architecture designed for full and fast reprogrammability. Its high density provides optimized silicon area, low consumption and high speed. The I/O interfaces are completely flexible. FlexEOS macros come with a software tool suite for rapid compilation of new applications, which can then be dynamically loaded into the FlexEOS core.

The architecture is organized as a hierarchical multi-level interconnect. Digital logic is implemented in an array of SRAM-based logic elements called Multi Function logic Cells (MFC). The MFC is a 4 input/1 output programmable structure associating a 4-input Look-Up Table (LUT) and storage element (flip-flop). An MFC is equivalent to approximately 10 equivalent ASIC gates. FlexEOS macros are available from 1K to more than 100K MFCs, which equates to roughly 10K to 1M ASIC gates.

The core I/Os are symmetrical, thus predefined I/O placement is never a constraint when mapping a new function. Any input can be used as a clock input, which allows multiple independent clock domains.

A typical core comprising 3,000 MFC elements, offering an equivalent ASIC gate capacity of 30,000 gates (200K FPGA equivalent gates), has a size of 8 mm2 on the ST HCMOS8 0.18u process. Its maximum measured frequency is 340MHz for a typical system clock of 150MHz, with low power consumption (standby current less than 100µA and 100mW running 120 counters at 66MHz).

In 130nm technology, a 3,072 MFC FlexEOS core has a size of 4.5mm2, and a configuration file of 28Kbyte which can be loaded in 0.5ms at 100MHz. The maximum measured speed of this core is 700MHz.

M2000 argues that FlexEOS macros stand out from similar products due to their patented architecture, which is based on a symmetrical interconnection network. This architecture provides high density, high performance and low power consumption. I/O assignment is completely flexible; any I/O can be defined as a low skew clock. M2000 also provides easy-to-use, automatic compilation software.

The FlexEOS macro is portable to any CMOS technology and has been proven on ST’s HCMOS8 0.18µ and HCMOS9 0.13µ process. ST and M2000 have validated the methodology with a series of test chips and pilot projects. The FlexEOS business model is based on a license fee and royalties related to the production volume and type of macro.

The biggest potential competitor is IBM’s ASICs featuring embedded Xilinx FPGA technology. M2000 believes that FlexEOS offers better density, higher performance, and faster reconfiguration time with a compact configuration file as well as flexible I/O assignment and scalability. Partners include Mentor and Synplicity for EDA tools and Accent for design services.

Frederic Reblewski, Chairman and CEO (previously the founder of Meta Systems, an emulation machine developer that was acquired by Mentor)

Olivier Lepape, Director R&D (20+ years of experience at ES2/ATMEL, Matra, Dune and Meta Systems)

Gabriele Pulini, VP for Marketing and Sales (previously held worldwide marketing management responsibilities at Mentor)