ChipWrights was founded in October 1999 to develop “a new class of DSP-based devices called visual signal processors (ViSPs)” for mobile imaging applications. In April 2000, ChipWrights closed $4.5 million in Series A financing led by Techfund Capital, and including Chase Venture Partners and Mitsui COMTEK. In January 2002, ChipWrights completed an $8.7 million Series B round led by BancBoston Ventures and including new investors Band of Angels VC Fund, MTDC Ventures, and New England Partners Capital, as well as existing investors JPMorgan Partners and Techfarm.

ChipWrights has developed the visual signal processor (ViSP) family of fully programmable, low cost, low power, and very high performance DSP/RISC microprocessors for the mobile digital imaging and video markets. Target applications include web-, PDA-, and cell phone-based cameras, digital still and video cameras, video transcoders, photo kiosks, and digital color copiers. The ViSP family frees designers from the restrictions imposed by fixed-function SoCs commonly used in consumer applications and offers significantly better cost, power, and performance compared to multi-processor and VLIW architecture-based devices commonly used in commercial applications.

The ChipWrights core DSP technology is based on a Very Dense Instruction Word (VDIW) architecture, which supports a single programming target and is designed to accelerate applications that can take advantage of data level parallelism. This course- grained architecture supports between 2 and 16 parallel DSP units and can deliver up to 64 MACS/cycle at less than 1 watt. Vector processor techniques simplify programming and allow the number of execution units to be abstracted from the programmer.

The architecture integrates multiple 32-bit, fixed-point imaging DSP engines and a 32-bit RISC processor. The processor is fully pipelined and issues one complex, single instruction multiple data (SIMD) instruction per cycle. The architecture is scalable, supporting 2, 4, 8, or 16 parallel DSP imaging units. Multiple processors can be chained together in a glueless fashion to supported distributed multi-processor implementations. The chip multi-processing architecture will also support multiple CWvx cores on the same die for high-end “pure-DSP” applications.

The device is based on a SIMD architecture with true Vector properties, unlike other SIMD approaches, such as Intel MMX style sub-word parallelism. The VDIW architecture executes several operations with every instruction, enabling many algorithms to be executed in fewer cycles as well as minimizing code, instruction cache, and decode logic sizes. The data memory architecture achieves 4.25 gigabytes of bandwidth internally, without the cost, complexity, or uncertainty associated with a cache-based design.

The CW4011 ViSP, the first member of ChipWrights’ ViSP family, is claimed to be the first application specific DSP optimized for image and video processing. The CW4011 is claimed to be the only device in its class that can achieve real time video main level, main profile (MP@ML) MPEG2 encoding at cost and power points suitable for battery operated, portable digital image capture devices. At over 4000 MIPS, it is claimed to be twice as fast as similar solutions based on general-purpose DSP architectures. And at 0.10mW/MIPS, it supports the low power requirements of battery-powered devices.

The CW4011 is based on a 32-bit fixed-point processor core comprising a RISC microprocessor and a scalable array of SIMD/DSP processing units. The CWv8 processor core includes a vector array of fully pipelined DSP units that support 32 multiply accumulates per cycle. It has traditional vector features such as strided and scatter-gather memory accesses, conditional operations, code-independence from the number of datapaths and uniform memory. It enhances vector processing with features such as end-of-array handling, run-time variable numbers of datapaths, table operations, and unlimited conditional nesting.

The CW4011 supports a 16/32-bit SDRAM interface and a 16-bit host/peripheral interface. It also includes separate 16-bit video-in and video-out ports that support simultaneous data transfers at 100MB/sec. Other features include a 3-channel DMA controller, 3-wire SPI serial interface, UART, JTAG/SCAN unit, 16 GPIO, and 3 timers.

According to ChipWrights, competitive solutions, based on either multiple processing cores or fixed function computational accelerators that limit flexibility, are both cost- and power-prohibitive. The CW4011 is fully C programmable and can support real time MPEG2 and MPEG4 video encoding in a completely flexible manner. It supports real time video decode of VGA MPEG4 streams at 30 frames per second and MPEG2 MP@ML. It has enough performance to support simultaneous real-time CIF MPEG4 (I+P frames) encode and decode for high quality, low bit rate videophone applications.

The CW4011 supports a digital still camera (DSC) pipeline for CMOS and CCD sensors, including JPEG compression running at 12 megapixels/sec, which is claimed to be more than twice the performance of competitive solutions based on fixed function accelerators and general purpose DSPs. This enables continuous burst shooting in three megapixel digital cameras at 4+ fps, with 16MB SDRAM, or capture of full motion, 30 fps, JPEG images at VGA resolution. In standalone operation, the CW4011 supports JPEG compression at over 20 megapixels/sec. It also supports emerging DSC standards such as wavelet-based JPEG2000, which enables better compression without image degradation.

The CW4011 ViSP offers designers a single programming target and is available with a SDK that includes an optimizing C compiler, a cycle accurate software simulator, a visual (JTAG) debugger and assembler, and a performance profiler – all based on Metrowerks CodeWarrior Integrated Development Environment (IDE). The CW4011 is designed to be the main system controller and is supported by the Accelerated Technology Nucleus PLUS RTOS. It can also operate as a coprocessor and connects gluelessly to many 8/16-bit microcontrollers. Multiple CW4011s can be chained together through the high-speed video ports to form a distributed multiprocessor system for video transcoding, digital cinema processing, and other high performance video and image processing applications.

The CW4011 will be offered in 200, 233, and 266MHz speed grades. Samples are available now; production volumes will be available in Q3. Pricing begins at less than $20 in quantities of 10Ku.

Brian Fitzgerald, President and CEO (previously managed IBM’s ASIC development organization, Director of Worldwide Field Applications Engineering at IBM Microelectronics, and most recently VP of Engineering at Xionics Document Technologies)

John Redford, CTO (previously the lead architect at Pixel Magic, a division of Oak Technology, where he designed their imaging JPEG codec and image processing DSP family)

Steven Wilson, VP of Marketing (previously senior manager of the controller and ASIC development groups at Xionics and VP of Engineering for Databook)

Patrick Chiumiento, VP of Sales and Business Development (previously with Chips and Technologies and IBM Microelectronics and most recently VP of Sales and Marketing at N*Able Technologies, which was acquired by Wave Systems)

Dawn Fitzgerald, VP of Engineering (most recently Director of Engineering for Motorola’s router business unit)