Rick Bleszynski, Ash Dhar, Charles Gershman, Tony Chiang, and Man Trinh founded Bay Microsystems in Q4 1999 “to be the leader in providing ultra high performance, highly scalable, intelligent Internetworking Processors.” The company raised $4M in initial funding from Selby Venture Partners, Alliance Venture Partners, and Needham Capital. In Feb. 2001, Bay closed another round led by Thomas Weisel Partners bringing the total capital raised to date $26 million. The company has 51 employees.

According to Bay Microsystems, the current generation of NPUs have “hit the wall” at 10 Gbps. They have significant memory latencies coupled with non-deterministic traffic patterns. They are not scalable, have exceedingly high pin counts, and struggle to support contexts changes on every packet.

Bay Microsystems is developing a deterministic, superscalar, pipelined internetworking processor that delivers 10/20/40 Gbps guaranteed sustained line rate performance, regardless of traffic patterns and network services. The process uses a simplified programming model, a unified packet/cell-centric superscalar, pipelined architecture, AnyMapper, Vertical Data Processing, and Vertical Instruction Processing.

Target markets include high-end edge switch/routers that require high packet performance, metro/web switches that support value added features like VPNs, load balancing and IP services, broadband access products that require traffic engineering, provisioning, and support for legacy protocols, voice gateways that utilize legacy TDM switching, and optical interworking products.

The processor is based on a multi-stage pipeline architecture consisting of a Multiphase Dynamic Classifier, Flexible Transformation Editor, Wire-Speed Packet/Cell SAR, Queue Manager, and Traffic Manager. The processor performs Internetworking, Routing, MPLS Switching, SARing, Policing, and Shaping/Queuing. The device supports 31.25 million packet/sec sustained packet processing performance, without degradation under load, 32 Gbps sustained data throughput, and 83 million lookups/sec expandable to more than 300 million lookups/sec.

A single chip can support full duplex 10 GE wire speed operation, sustaining 29.6M packets/sec based on 64 byte packets with 20 byte gap. Or it can support simplex OC-192c wire-speed operation sustaining 25 million packets/sec based on 40 byte packets.

The company offers a cycle accurate simulator for system configuration, software coding, device debug, fault isolation, performance analysis, and functional analysis. A 19” rackmount development system features a 80 Gbps switch fabric, 10 Gbps full-duplex line cards, and a modular mid-plane architecture with an assortment of PHY/Framer cards like 2xOC192, channelized OC-48, 10 GE, etc. The SDK and documentation are available now. Performance has been simulated and proven beyond 10 Gbps. Post layout simulation is in progress.

The network processor landscape is ridiculously crowded with the likes of Azanda, Acorn, Agere, EZ-Chip, Zettacom, AMCC, Silicon Access, Cognigine, Internet Machines, Vitesse, and Xelerated Packets, to name just a few. Bay claims to have the only solution that combines both network processing and traffic management, while sustaining 10 Gbps line rates. According to Bay, Xelerated Packets is the most similar competitor, with its super wide and deep pipelined architecture, however Bay believes that its device will come to market years before Xelerated’s. We’ll see…

Bay’s initial single chip solution will sustain guaranteed line rate performance of 10Gbps. Shortly thereafter, Bay will deliver a single chip 20 Gbps solution, followed by single chip 40 Gbps solution. In the coming months, Bay will announce numerous strategic alliances with complementary communications IC technology leaders in support of end-to-end OEM solutions. The device is fabricated in a 0.18u CMOS process. Customer samples are anticipated for mid-late March, at which time Bay will disclose product specifics.

Rick Bleszynski, Chairman & CEO (previously the founder, VP of Engineering, and CTO at Softcom, which was acquired by Intel. He also created the ATMizer product family at LSI Logic.)

Tony Chiang, VP of VLSI Engineering (previously VP of VLSI Design Engineering at C-Cube)

Ash Dhar, President (previously held executive management roles at Xilinx, S3, Global Village Communications, Rise Technology, and Paradigm)

Charles Gershman, VP of Marketing & Sales (previously VP of Sales and Business Development at Softcom and VP, Sales at Actel)

Man Trinh, Director of Systems Engineering/Architect (previously involved with the architecture and implementation of the GigaBlade network accelerator at Softcom)