0-In (zero-in) was founded in 1996 to develop products and services that help IC design teams quickly find functional errors in their designs. The company's technical team includes expertise in formal verification, simulation, coverage analysis, high-level synthesis, and ASIC design. 0-In also has a technical advisory board of industry and academia experts. 0-In has 14 employees and expects to be at 20+ employees by year-end. Its products will be introduced within a year and will focus on finding late-stage functional errors in HDL-based designs. The company is privately funded.

IC design teams spend over half of their effort on verification, much of it trying to find the last 20% of the bugs. 0-In is developing "assertion synthesis" and "directed search" technologies that will systematically search for tough bugs resulting from complex control interactions. Based on recent research on the FLASH multiprocessor at Stanford, 0-In studied bugs in errata sheets, bugs that caused silicon turns, and bugs found late in the design cycle and identified a common signature, called a "register leak," for up to 50% of the toughest bugs. This signature is data loss or data corruption in a shared register or shared register file due to improper interactions between a pair of controllers. Assertion synthesis automaticly creates a checker module that detects register leaks and a wide range of other bugs near their sources. Assertions provide testbench independence and low detection latency. Directed search is a hybrid of simulation and formal verification that exercises extremely difficult-to-test control interactions call "pair arcs." Once a design functions correctly under typical operating conditions, designers can use directed search to massively stress-test the designs. 0-In is working with several design teams and EDA vendors to ensure that its technology will fit into current design flows.

This year, EDA activity can be summed up in one word - verification. 0-In is carving out a niche by developing systematic technology that focuses on finding the toughest bugs in ASIC and IC design. 0-In plans to support Verilog and VHDL on all major platforms. The company expects to have direct sales channels in the US and Europe, and a distribution partner in Japan. Given ever increasing design complexities and ever decreasing time-to-market goals, there should be a wide audience for its products.

Dr. L. Curtis Widdoes, Jr., Chairman, CEO & President (co-founder of Logic Modeling & Valid)

Steven White, VP of Operations (formerly VP of Design Verification at Synopsys, co-founded Logic Modeling)