3DSP was founded “to develop and license high performance, low power, low cost, general purpose DSP IP cores and related SOC solutions for Internet appliances.”

The company has developed a super-scalar instruction multiple data (SuperSIMD) DSP, the SP-5, which can operate at 150 MHz at 2.5V and performs 2.4 Giga RISC ops/sec. The superscalar architecture can execute 2 instructions per cycle, each of which can operate on multiple data. The hardware automatically detects, and handles all data and pipeline hazards. The architecture uses a high-bandwidth, 4-access per cycle on-chip SRAM. The core includes an on-chip debug port, full scan and JTAG. 3DSP also provides a development system including debugger, emulator, C simulator, C compiler, Assembler and Linker.

Peak performance for the SP-5 is 600M 16x16 MACs per second. It can execute 16 RISC equivalent instructions per cycle in 16-bit format or 24 per cycle in 8-bit format achieving 2.4Gops/sec and 3.6Gops/sec respectively. The SP-5 can perform an 8x8 JPEG DCT in 300 cycles compared to the TI C54X, which requires 3000 cycles. The code size is 800 bytes compared to the TIC6x’s 2000 bytes. A 256 point 2bit butterfly FFT requires 4,205 cycles compared to the TIC6x’s 4,250 cycles. The SP-5 is claimed to have similarly superior performance compared to ADI ADSP-21xx, Lucent DSP16xx and DSP Group OAK DSPs.

The core is claimed to be 100% synthesizable and can be ported to any process. The estimated DSP core die size is 1.6 – 2.4 mm2 using a 0.25u, 4-layer metal process. With USB, 32KB SRAM, SDRAM controller, traffic controller, CDDE interface, UART, debug port, and parallel interface the die size is 4mm2. The core’s power consumes approx. 0.3W at 2.5V.

The DSP core includes microcontroller features, enabling it to be used as a microcontroller as well as DSP. The on-chip intelligent system bus controller supports multiple channels, multiple priorities and is configurable for SOC applications. 3DSP has also developed other key technologies including USB, pipelined high throughput SDRAM controller, CDD/CMOS sensor interface, UART, timer, GPIO, PLL, and crystal oscillator.

3DSP’s long term goal is to provide a family of DSP cores for high performance and low power, low cost applications. By 2000 3DSP plans to offer 4 additional devices: The SP-3, a 16-bit low power, low cost 100MHz DSP for low-end consumer applications. The SP5-II will achieve 200MHz, 800 million 16x16 MACs/sec performance or 4.8Giga RISC ops/sec in 8-bit data format. The SP10 is a 200MHz dual-processor DSP capable of 1.6Giga 16x16 MACS/sec. The SP20 will operate at 500MHz, and achieve 1000 million 16x16 MACs/sec.

The SP-5 is claimed to achieve 3 – 5x the performance, with the same cost and power per MIPS, of the C54x. 3DSP claims it has the same performance as the C6x with 75% lower power consumption, is easier to program, and uses less memory. It is 100% synthesizable, has very low power consumption, high code density, ease of programming, and is C compiler friendly.

3DSP believes that ease of programming will become the most important concern for programmers, as opposed to compatibility with legacy generations. The SuperSIMD architecture is claimed to be C compiler friendly and much easier to program then VLIW architectures, while achieving VLIW-like performance with high code density and low power consumption. Target applications include 3rd generation wireless phones, next generation mega-pixel digital cameras, multi-channel VoIP Internet phones, ADSL modems, and application such as voice recognition and speech synthesis.

Kan Lu, president & CEO

Chongjun "June" Jiang, VP of DSP Development & CFO

Duane E. Smith, VP of product marketing

Hong Helena Zheng, VP of ASIC engineering