Professor Wayne Dai founded Ultima in 1995 to develop interconnect tools for DSM IC design. Professor Dai is a former technical advisor to Cadence and an industry expert in the field of interconnect synthesis. Board members include Professor Ernest Kuh, Dr. Andrew Yang, and Dr. King Tai. Professor Kuh, the former Dean of the College of Engineering, UC Berkeley, is a former director of ECAD, Cadence, and Arcsys. Dr. Yang is a Research Associate Professor, Electrical Engineering, at the University of Washington, and previously founded Anagram. Dr. Tai, a Fellow at Bell Labs, is the originator of silicon-on-silicon MCMs. In Aug. ’98, Ultima closed a multi-million round of financing from VentureStar of San Jose and other investors. The company does not anticipate additional capital requirements at this time. Ultima has about 20 employees.

Ten years ago 90% of the delay on a chip was due to transistor performance. Today the number is about 50%. In the near future 90% of the delay will be attributed to interconnect. Most existing EDA tools are “gate or transistor-centric.” Ultima is focused on providing best-in-class tools and technologies to explore, analyze, and optimize interconnect issues in DSM designs. The company has developed 3 tools: Millennium for fast DSM delay calculation; Nautilus for 3D net parasitic extraction; and Predator for parasitic reduction.

Millennium computes both cell and interconnect delays for interconnect dominated DSM IC designs and enables orders of magnitude faster DSM delay calculation, achieving SPICE-like accuracy for large cell-based designs. It reads a post-layout netlist or a pre-layout netlist and cell timing library together with I/O specifications and outputs a file including point-to-point net delay as well as pin-to-pin cell delay. Other outputs include rise and fall times and skew for each net. Millennium is claimed to achieve accuracy within 3% of SPICE simulation. The tool can also generate path-timing constraints to drive place and route.

Nautilus is a fast and accurate 3D parasitic (resistance and capacitance) extraction tool for chip and block level interconnects. 2D RC extraction methods can have unpredictable accuracy when applied to long complex nets. The best solution for accurate parasitic extraction is based on a 3D field solver. However, a 3D field solver requires powerful computers and long execution times for even modest-size circuits. Nautilus is able to extract chip level nets with accuracy close to 3D field solvers at speeds approaching 2D extraction. Ultima’s proprietary field solver technology is claimed to deliver a 20-30X speed improvement over industry standard 3D field solvers, with no compromise in accuracy.

Ultima’s solver is based on Geometric Independent Measured Equation of Invariance or GIMEI technology, developed by the company’s founder, Wayne Dai, and his students. The GIMEI field solver delivers a 20-30X-speed improvement over industry standard field solvers. Nautilus takes about twice the time needed by 2D or quasi-3D RC extractors, and has lumped and distributed coupling capacitance accuracy within 10% of industry standard capacitance solvers.

Predator is a parasitic reduction tool that handles huge RC netlists, including networks with 2D or 3D mesh structures, resulting in improvements in simulation performance with no loss in accuracy. Predator reduces extracted parasitic data to decrease the computational and storage burden of IC simulators with typically less than 1% accuracy loss. Predator can improve SPICE simulation run time by 140 times and reduce resistor and capacitor data by 50% to 99%.

Ultima was chosen in November 1996 to be part of SEMATECH’s Chip Hierarchical Design System (CHDS) along with Bell Labs. CHDS is part of SEMATECH’s effort to solve the problems of designing circuits in process technologies of 0.25u and smaller. Ultima’s products can be used individually as plug and play modules in existing extraction and verification flows, or can be tightly integrated through each tool’s API.

Future products will tackle deep submicron signal integrity and timing robustness solutions. Customers include AMD, Cirrus, H-P, Hitachi, IBM, Micron, MMC Networks, Motorola, NEC, Neomagic, Oak, TI, and Toshiba, amongst others. Ultima’s primary competitor is Avant! Ultima believes that it has superior technology, a more focused effort in deep submicron signal integrity and timing robustness, and a better fit with existing design flows. Ultima makes its technology available to select partners for use with their tools and develops and sells products independently as well. The company has partnerships with Synopsys, Cadence, Mentor, Sematech, and NEC.

Professor Wayne Dai, Founder & Chairman