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Sitera (formerly Fusion Micromedia) -- Network Processors
 
Founded: Nov 1996
Status: Acquired by Vitesse 4/00
Issue(s): 1/98, 5/00
www.Sitera.com
1820 Lefthand Circle
Longmont, CO 80503
Tel: 303/651-1000
Fax: 303/651-1199

Sitera was founded in Nov. 1996 by Steve Flannery, Jonathan Huie, Cindy Lindsay, Steve Sheafor and James Wei as Fusion MicroMedia (see Jan. ’98). Fusion’s original mission was to develop SOCs for high throughput applications in which its MultiStreaming bus architecture technology can enhance system performance. In 1997, the company changed its name to Sitera and announced its new mission to develop Packet Processing chipsets.

The company closed $10 million in first- round funding in July ’98 from InterWest Partners, Matrix Partners, Greylock, and Sevin Rosen. In June ’99, Sitera raised $14 million in second-round funding led by Berkeley International Capital and including the first round investors. A third round of capital will be sought in May. Sitera currently has 75 employees.

Sitera’s Network Acceleration Platform includes programmable network processors, Sitera’s SoftNet library of networking software, open interfaces to fabrics and peripheral media, and an integrated development system. Sitera recently announced its long awaited PRISM IQ2000 Network Processor Family, designed to deliver flexible, wire-speed packet processing at speeds ranging from N x DS0 to OC-48 with significant processing headroom to support advanced IP services. Sitera also introduced its hardware design and development system with software support libraries, a hardware evaluation platform, an I/O model kit, and Layer 2/Layer 3 reference application code.

The PRISM IQ2000 Network Processor family is based on multiple on-chip processors that perform deep packet processing for wire-speed multi-protocol routing, classification, filtering, state-oriented inspection, encryption, policy enforcement, traffic shaping, multicast management, address translation, and other operations.

Each PRISM IQ2000 processor features 4 multi-context, 200 MHz RISC-based, packet-processing engines. The PRISM IQ2000 also employs multiple, embedded co-processors including Multicast Management, Lookup, Classification, DMA, Context Control, Order Management, Overflow Control, High Speed Transaction-oriented Memory, and QoS Co-processors.

The PRISM IQ2000 addresses up to 2 gigabytes of RDRAM memory for data and table storage. Through the Rambus interface, the Sitera network processor is able to support a 12.8 Gbps data path to RDRAM devices. Each member of the family is equipped with four Utopia-like 16- or 32-bit FOCUS busses for data transfer operations with external peripheral devices and switch fabrics. The FOCUS interfaces each provide a peak bandwidth of 3.2 Gbps full-duplex at clock rates up to 100 MHz.

The PRISM IQ2000 integrate four QoS engines per chip for implementation of QoS and queue management algorithms including Weighted Fair Queuing (WFQ), Rate Limiting Queues, Weighted Random Early Discard (WRED and RED), RED In/Out of Profile (RIO), Round Robin (RR), and Weighted Round Robin (WRR).

The PRISM IQ2000 family consists of six chips. Each device integrates either 16 Kbytes or 32 Kbytes of on-chip memory. The S21132 series is targeted at the “Intelligent Edge” of the optical core and features two 32-bit FOCUS interfaces. The S21102 series is targeted at server load balancing and service-enabled Ethernet aggregation and features two Gigabit Ethernet MACs and two 16-bit FOCUS interfaces. The S21100 series is targeted at service-enabled aggregation platforms that provide lower speed aggregation at rates ranging from DS0 to OC3 and integrates four 16-bit FOCUS interfaces.

The PRISM family supports multiple control plane (route processing and management operations) processors, ranging from low-cost to high-performance MIPS, PowerPC, and other RISC implementations. Processor partners include IDT, NEC, QED, and others. Sitera claims that this gives its network processors more flexibility and a performance and cost advantage over network processors that require route processing software to be ported to on-chip proprietary processors.

Sitera believes its special instructions, optimized for packet processing, are roughly 3x as efficient as the same functions implemented using a standard RISC instruction set. The PRISM IQ2000 chipset provides approximately 40% “headroom” when operating as an RFC-1812-compliant router and driving 5 million packets per second with two gigabit streams. With a one gigabit stream, the platform provides approximately 60% additional headroom. This headroom allows vendors to perform additional, higher layer, packet processing operations.

Sitera’s development suite provides a graphical environment for system simulation, hardware assisted debug, and an integrated environment for system regression and performance testing. Sitera’s SoftNet library includes drivers, models for emerging network services, APIs and core switching and routing algorithms. PRISM is designed to interface to a number of peripheral media and fabrics as well as specialty coprocessors such as encryption, compression, and classification processors.

Partners include IDT, QED, Phase2 - A Nortel company, Wind River, Hi/fn, Rainbow Technologies, Chrysalis – ITS, Ficon, SwitchOn, and Power X.

Sitera’s roadmap is focused on two areas. The first is obvious improvements in processor speeds, scaling to OC192 or OC48 with additional headroom, based on die shrinks, as well as incremental software development environment improvements. The second focus area is connectivity between the FOCUS interface and a variety of external elements. Sitera plans to introduce ICs and IP for FOCUS to POSPHY, FOCUS to CSIX, and more. An OCTALMAC will be introduced in Q2.

The company’s primary competitors are MMC, Intel, and C-Port. According to Sitera, its strengths are its software development environment, use of RDRAM, flexibility to use a variety of ind. std. control plane processors, hardware acceleration for queuing and QoS, and low power. The software development suite enables a programmer to focus on one stream of data, while the hardware determines context switches and figures out how to direct the stream to the 4 embedded cores.

UMC provides wafer fabrication services. Samples are available now; production units will be available in Q3. Prices start at $250 per unit. Sitera has about 12 customer engagements under way with tier 1, 2, and startup accounts, including Nortel according to the rumor mill.

Late breaking news - Vitesse has acquired Sitera for $750 million in stock. Not bad, considering the the C-Port and Agere deals were in the $400 million range.

Steven Flannery, Founder, President and CEO (formerly Executive VP of Operations at MDI, VP of R&D of Motorola’s Mobile Data Division, and VP of Development of Norand)

Dr. Stephen Sheafor, Founder, Executive VP of R&D (formerly founder & CTO of Cornerstone Imaging)

Wade Appelman, VP of Marketing (formerly Senior Director of Product Marketing & Product management at Cabletron)

Tim McCarthy, VP of Operations (formerly Senior VP of the Semiconductor Division of Symbios)

Larry Woodson, VP of Sales (formerly VP of Marketing for AMCC and VP of Marketing for Synopsys)



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