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Triscend -- Configurable Processors
 
Founded: May 1997
Status: Acquired by Xilinx 4/04
Issue(s): 9/98, 11/9
www.triscendcorp.com
301 North Whisman Road
Mountain View, CA 94043
Tel: 650-968-8668
Fax: 650-934-9393

Triscend was founded in May 1997 to develop a series of configurable processors - single-chip combinations of industry-standard microprocessors, programmable logic, memory and a dedicated system bus. The company has completed seed and first round financing for a significant but undisclosed amount. A second round of financing will be completed soon.

Triscend recently introduced its E5 Configurable Processor Family and the FastChip Configurable Processor Development System. The E5 family is based on a performance-enhanced 8032 microcontroller rated at 10MIPS at 40MHz. Future families will be based on other leading 8-bit and 32-bit microprocessors and DSP cores. The E5 family consists of 4 devices, all sharing the same architecture, but differentiated by the amount of programmable logic, system RAM and user I/O. The family offers up to 64Kbytes of on-chip RAM and up to 3,200 CSL cells (about 40K logic gates). A dedicated internal bus offering 40Mbytes/s transfer rates provides stand-alone operation from a single external memory that holds the processor code and CSL configuration data. The TE520 will sample in December; prod. by March '99; $55 in hundreds. The TE505 will cost less than $8 in high volumes in 2000.

Device CSL Cells RAM I/O Samples

TE505 512 8Kx8 123 1Q99

TE512 1,152 16Kx8 187 3Q99

TE520 2,048 40Kx8 251 4Q98

TE532 3,200 64Kx8 315 2Q99

Triscend's programmable logic is called Configurable System Logic (CSL) and is based on SRAM-based Configurable System Logic cells (CSL cells). The CSL matrix is a collection of CSL cells, interconnect routing, debugging circuitry and CSI Socket connections optimized for tight integration with the system and CSI bus. The CSL matrix features more than 3,800 flip-flops and 300 programmable inputs and outputs.

The Configurable System Interconnect (CSI) bus consists of a 32-bit address bus and an 8-bit data bus. The CSI Socket is a processor-independent, open-system interface between the (CSI) bus and the programmable logic. The CSI Socket defines the physical signaling interface between the CSI bus and the CSL matrix and the communication protocol between soft peripherals and the CSI bus. The CSI Socket enables Triscend's "derivative on demand" functionality, and ensures the reuse of soft peripherals across all Triscend CPU families. Triscend plans to openly document the CSI Socket so that users and 3rd party IP developers can create application solutions that will operate on all Triscend Configurable Processor families.

The Configurable Processor Windows-based software development system manages the processor configuration and oversees the entire development flow. Designers can "instantly" create a processor derivative by selecting parameterizable "soft" peripherals from a Triscend library, then "dragging and dropping" them into the CSL Matrix. The designer then uses existing development tools, which treat the "soft peripherals" as though they were fixed functions, to complete the embedded system project. Triscend is partnering with EDA vendors to enable customers and independent IP developers to create soft peripheral logic.

Many vendors have "toyed" with the configurable processor concept, although none have launched products due to the system and software level difficulties of integrating programmable logic with a processor. SIDSA, a startup in Spain (7/98 issue), has launched a similar device that even includes analog functions. And WSI has made a business of providing chips that integrate programmable logic, SRAM, FLASH, and peripheral functions. Triscend appears to have a well designed, comprehensive approach that is scalable and enables design reuse. The company already has several early customer partners. The E5 family is fabricated at UMC on a 4-layer metal, 0.35u process. Sales reps. have already been hired in the U.S. and Japan. Asian and European sales channels will be established in early '99.

Stanley Yang, President & CEO
Danesh Tavana, founder and VP of engineering (formerly dir. of engineering for FPGA design and soft-core development at Xilinx)
Chris Balough, VP of marketing
Richard Christopher, exec. VP and COO



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