Tensilica was founded in July 1997 to develop application-tailored, synthesizable microprocessor IP for single chip systems in high volume markets. Tensilica has received $13M of funding in two rounds. Major investors include Oak Investment Partners, Worldview Technology Partners and Foundation Capital.
Tensilica was founded by Chris Rowen, Harvey Jones, and Bernie Rosenthal in July 1997 to "address the fast growing market for application-specific microprocessor cores and software development tools in high volume, embedded systems." The founders provided first round capital, and a second financing round was completed in 2Q '98 with Oak Investments, Worldview Technology, and Foundation Capital bringing the total financing to over $13 million. Tensilica is well capitalized for now and does not anticipate additional capital requirements for some time. The company has more than 30 employees.
Tensilica recently unveiled what it claims is the first configurable and extensible microprocessor architecture and development environment. The technology enables embedded system designers to rapidly build highly differentiated and optimized synthesizable processor cores for use in ASIC-based products. Using the company's Xtensa Processor Generator, designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements. TenSilica claims that it can implement substantially new processor designs from configuration to layout in less than eight hours.
Tensilica believes that in today's emerging applications, the flexibility in the implementation of the processor subsystem is critical. Xtensa is a processor architecture and tool set that helps embedded designers create, verify and implement differentiated processor solutions. The Xtensa Solution is a complete embedded microprocessor development solution consisting of a configurable ASIC processor core and software development tools including a C/C++ compiler, assembler, linker, cycle accurate instruction set simulator and code profiler.
Xtensa consists of a new processor architecture, a powerful instruction set and an instruction set extension mechanism. Using Xtensa, developers simultaneously tune both application software and processor hardware to meet specific speed, power, and feature goals of their application. The result could be as much as a 20x improvement in the performance of key software algorithms, and performance that can be translated into lower power, higher speed or increased functionality.
Tensilicia has focused on the application-specific extensibility of the core processor, and methods for hardware/software integration and co-design to optimize designs and accelerate time-to-market. The Xtensa Processor Generator uses a library of base processor designs and a function library of pre-verified or designer-defined peripherals to create ultra small and highly efficient new architectures. Using the Tensilica Instruction Extension (TIE) Language, designers can describe a function or set of functions that represent the behavior of an instruction that is not part of the Xtensa base instruction set. The Xtensa processor generator will simultaneously build a hardware representation and generate a C/C++ compiler, assembler, debugger and instruction set simulator with full intrinsic support of the new instructions. The output of the Generator includes a GNU-based software tool chain that provides synchronized extensibility to the processor hardware, and efficient RTL synthesis, test suites, and placement information.
The Xtensa 32-bit architecture features an instruction set optimized for embedded designs. The base instruction set has a 32-bit ALU, up to 64 general-purpose physical registers, 6 special purpose registers, and 77 instructions. The architecture provides optional packages of instruction sets and states for caches, a windowed register file, 16-bit compressed instructions, exceptions, timers, interrupts, debugging, designer-defined instructions, co-processors, integer multiply, and a filter DSP unit. Xtensa's patent-pending 16/24-bit encoding with 4-bit register fields reduces the average number of bits per instruction and the static number of instructions required to represent a program. Zero overhead loops can lower branch penalties anywhere the source code calls for a loop to be executed a predetermined number of times. Xtensa utilizes a new type of register window that can cut code size by an additional 10% by reducing the need for register shuffling. Funnel shifts can also save on code size by providing more functionality in a single instruction.
TenSilicia claims that its solution goes way beyond the typical synthesizeable HDL processor core or graphical interface. It is a tightly integrated hardware and software development environment that allows any changes in the hardware to be immediately verifiable and accessible by software tools like C/C++ compilers, assemblers and debuggers. It creates a method for designers to reliably and quickly add specialized coprocessor instructions and interfaces, and have them instantly recognized as "native" by the entire software development tool chain.
Xtensa is fully synthesizeable and technology portable. The processor core requires approx. 25 K gates and typically operates at greater than 250 MHz in a 0.25u process. The base configuration requires approx. 1.0 mm2 in a 0.25u standard cell process. The low power core consumes less than 0.5 mW/MHz in the base configuration. Tensilica offers two delivery options. The standard option provides a firm macro in Verilog or VHDL RTL, and supporting EDA tool scripts, test suite, placement guidelines and the customized software tool chain. The ruggedized option provides a hard macro in the form of a Verilog/VHDL netlist, GDSII using the target vendor's cell library, a test suite and the software tool chain. Prices are based on a licensing fee per design plus per unit royalties. Licensing fees start at $350K.
Xtensa is targeted at high volume applications such as digital cameras, office automation products, wireless communications devices, datacom and telecom protocol processing, and other consumer electronic products. Tensilica has partnered with many companies to ensure support for its customers, including Altera, Arcadia Design Systems, Artisan Components, Avant!, Cadence, Integrated Systems, Synopsys, Virage Logic, Virtual Silicon Technology, and WindRiver. Tensilica is working closely with a number of customers including Zilog and Silicon Spice. Additional customer announcements are anticipated soon. Production silicon containing Xtensa cores will be introduced in late Q2 or early Q3.
Harvey Jones, Jr., Chairman (Chairman of Synopsys)
Chris Rowen, Ph.D., President and CEO (formerly VP for Microprocessor Development at MIPS. Most recently, VP/GM of the Design Reuse Group of Synopsys)
Beatrice Fu, VP of Engineering (formerly Director of the Microcomputer Software Lab at Intel)
Bernie Rosenthal, VP of Marketing and Business Development (formerly Director of Marketing for the Silicon Architects Group of Synopsys)
Keith Van Sickle, CFO (formerly GM of the European Manufacturing and Technology Center at Silicon Graphics)
Earl Killian Chief Architect (formerly Director of the Architecture Group at Silicon Graphics. Also a founder and CTO of QED and Director of Architecture for MIPS)
Ashish Dixit, Director of VLSI Design (formerly Director of Engineering, Consumer Products and Technology, for MIPS)
Dror Maydan, Ph.D. Manager of Software Development (formerly the Engineering Manager of the compiler group of Silicon Graphics)
John Ruttenberg Chief Engineer (Ex-Principal Engineer at Silicon Graphics. He was a founder of Multiflow Computer and inventor of VLIW architecture.)
Woody Lichtenstein, Ph.D. Chief Engineer (a manager of Compiler Development for SGI.)
Kaushik Sheth Chief Engineer (formerly Director of CAD at Stream Machine)
Albert Wang, Ph.D. Chief Engineer (Ex-Synopsys Fellow and one of the inventors of logic synthesis.)